Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
An FPGA may be configured when in a shut down mode, which halts operation of a user design instantiated in programmable logic of such FPGA. In this type of configuration, configuration bits may be checked, such as with a cyclic redundancy check (“CRC”) or an error-correcting code (“ECC”) validation, prior to be loaded in configuration memory.
In contrast to normal, “static” or “non-dynamic,” configuration, there is configuring or reconfiguring a user design while continuing operation of FPGA apart from such configuring or reconfiguring which is conventionally known as “dynamic partial configuration” or “dynamic partial reconfiguration.” For purposes of clarity, the phrase “dynamic partial configuration” is used herein to include either or both configuring or reconfiguring programmable logic dynamically. Heretofore, dynamic partial configuration could not be done with validation prior to such configuring. This meant that for dynamic partial configuration, validation could only be done by a readback of configuration bits already loaded into configuration memory. However, a bit which is in error and which is loaded may have adverse affects, such as for example one or more of: improper functioning of a user design; high current conditions; or permanent damage to an FPGA.
Accordingly, it would be desirable and useful to provide means to validate configuration bits prior to loading into configuration memory for dynamic partial configuration.